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? 2011 semtech corporation power management 1 SC202A 3.5mhz, 500ma step-down regulator with integrated inductor and digital programmable output features input voltage 2.9v to 5.5v output voltage 0.8v to 3.3v output current capability 500ma internal inductor programmable output voltages 15 high light-load efciency via automatic psave mode fast transient response temperature range -40 to +85c oscillator frequency 3.5mhz 100% duty cycle capability quiescent current 38a typical shutdown current 0.1a typical internal soft-start over-voltage protection current limit and short circuit protection over-temperature protection under-voltage lockout floating control pin protection mlpq-13 2.5 x 3.0 x 1.0 (mm) package lead-free and halogen-free weee and rohs compliant applications point of load regulation smart phones and cellular phones mp3/personal media players personal navigation devices digital cameras single li-ion cell or 3 nimh/nicd cell devices devices with 3.3v or 5v internal power rails ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC202A is a high efciency 500ma step-down regula - tor that includes an integrated inductor inside the package. the input voltage range makes it ideal for battery operated applications with space limitations. the SC202A also includes 15 programmable output voltage settings that can be selected using the four control pins, eliminating the need for external feedback resistors. the output voltage can be fxed to a single setting or dynami - cally switched between diferent levels. pulling all four control pins low disables the output. the SC202A operates at a fixed 3.5mhz switching fre - quency in normal pwm (pulse-width modulation) mode. a variable frequency psave (power-save) mode is used to optimize efciency at light loads for each output setting. built-in hysteresis prevents chattering between the two modes. the SC202A provides several protection features. these include short circuit protection, over-temperature protec - tion, under-voltage lockout, and soft-start to control in-rush current. these features, coupled with the small 2.5 x 3.0 x 1.0 (mm) package, make the SC202A a versatile device ideal for step-down regulation in products needing high efciency and a small pcb footprint. sc 202 a in ctl 3 ctl 2 ctl 1 ctl 0 sns out gnd v out 0 . 8 v to 3 . 3 v v in 2 . 9 v to 5 . 5 v c out 10 f c in 4 . 7 f control logic lines lx nc typical application circuit rev. 1.2
SC202A 2 pin confguration marking information ordering information device package SC202Amltrt (1)(2) mlpq-13 2.5 x 3.0 SC202Aevb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and rohs compliant and halogen-free. top view 1 2 3 4 5 6 7 8 9 10 11 12 13 lx lx lx out out out gnd in ctl 2 ctl 1 ctl 0 ctl 3 sns mlpq-13;f2.5fxf3.0,f13flead ja f=f58c/w tablef1fCfoutputfvoltagefsettings ctl3 ctl2 ctl1 ctl0 vout 0 0 0 0 shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.20 0 1 0 0 1.40 0 1 0 1 1.50 0 1 1 0 1.60 0 1 1 1 1.80 1 0 0 0 1.85 1 0 0 1 1.90 1 0 1 0 2.00 1 0 1 1 2.20 1 1 0 0 2.50 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 yywwf=fdatefcode xxxxf=fsemtechflotfnumber 202 a yyww xxxx
SC202A 3 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114-b. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb per jesd51 standards. absolute maximum ratings in (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 lx voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to v in + 0.5 other pins (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to v in + 0.3 output short circuit to gnd . . . . . . . . . . . . . . . . continuous esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions input voltage range (v) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5 operating temperature range (c) . . . . . . . . . . -40 to +85 thermal information thermal resistance, junction to ambient (2) (c/w) . . . . . 58 junction temperature range (c) . . . . . . . . . . . -40 to +150 storage temperature range (c) . . . . . . . . . . . . -65 to +150 unless otherwise specifed: v in = 3.6v, c in = 4.7f, c out =10f, v out =1.8v, t j(max) =125c, t a = -40 to +85 c. typical values are t a =+25 c parameter symbol condition min typ max units output voltage range v out 0.8 3.3 (1) v output voltage tolerance v out_tol i out = 200ma -2.0 2.0 % psave mode 1.5 line regulation v linereg 2.9 v in 5.5v, i out = 200ma 0.3 %/v load regulation v loadreg 200ma i out 500ma -1 %/a output current capability i out 500 ma current limit threshold i limit 800 1300 ma foldback current limit i fb_lim i load > i limit 150 ma under-voltage lockout v uvlo rising v in 2.9 v hysteresis 200 mv quiescent current i q no switching, i out = 0ma 38 60 a shutdown current i sd v ctl 0-3 = 0v 0.1 1.0 a output leakage current i out into out pin 0.1 1.0 a high side switch resistance (2) r dson_p i out = 100ma 250 m low side switch resistance (3) r dson_n i out = 100ma 350 electrical characteristics
SC202A 4 parameter symbol condition min typ max units switching frequency f sw 2.8 3.5 4.2 mhz soft-start t ss v out = 90% of fnal value 100 500 s thermal shutdown t ot rising temperature 160 c thermal shutdown hysteresis t hyst 20 c logic inputs - ctl0, ctl1, ctl2, and ctl3 input high voltage v ih 1.2 v input low voltage v il 0.4 v input high current i ih v ctl 0-3 = v in -2.0 5.0 a input low current i il v ctl 0-3 = gnd -2.0 2.0 a notes (1) maximum output voltage is limited to vin if the input is less than 3.3v. (2) measured from in to lx (3) measured from lx to gnd electrical characteristics (continued)
SC202A 5 typical characteristics efciencyfvs.fi out f(t a f=f-40c) load current ( ma ) e f f i c i e n c y ( % ) v out = 1 v , 1 . 8 v , 2 . 8 v , and 3 . 3 v 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 3 . 3 v 2 . 8 v 1 . 8 v 1 v efciencyfvs.fi out f(t a f=f25c) load current ( ma ) e f f i c i e n c y ( % ) v out = 1 v , 1 . 8 v , 2 . 8 v , and 3 . 3 v 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 3 . 3 v 2 . 8 v 1 . 8 v 1 v efciencyfvs.fi out f(t a f=f85c) load current ( ma ) e f f i c i e n c y ( % ) v out = 1 v , 1 . 8 v , 2 . 8 v , and 3 . 3 v 0 10 20 30 40 50 60 70 80 90 100 0 . 1 1 10 100 1000 1 v 3 . 3 v 2 . 8 v 1 . 8 v v out ( v ) e f f i c i e n c y ( % ) 4 . 2 v 5 . 0 v 65 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 3 . 6 v i out = 200 ma , v in = 3 . 6 v , 4 . 2 v , and 5 . 0 v e f f i c i e n c y ( % ) 4 . 2 v 5 . 0 v 65 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 v out ( v ) 3 . 6 v i out = 200 ma , v in = 3 . 6 v , 4 . 2 v , and 5 . 0 v v out ( v ) e f f i c i e n c y ( % ) 4 . 2 v 65 70 75 80 85 90 95 100 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 5 . 0 v 3 . 6 v i out = 200 ma , v in = 3 . 6 v , 4 . 2 v , and 5 . 0 v v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, t a = 25c unless otherwise noted. efciencyfvs.fv out f(t a f=f-40c) efciencyfvs.fv out f(t a f=f25c) efciencyfvs.fv out f(t a f=f85c)
SC202A 6 v in = 4.0v for v out = 3.3v, v in = 3.6v for all others. c in = 4.7f, c out = 10f, t a = 25c unless otherwise noted. frequencyfvs.ftemperature temperature ( c ) f r e q u e n c y ( m h z ) 1 . 0 v 3 . 3 v 3 3 . 1 3 . 2 3 . 3 3 . 4 3 . 5 3 . 6 - 40 - 20 0 20 40 60 80 100 2 . 8 v 1 . 8 v v out = 1 v , 1 . 8 v , 2 . 8 v , and 3 . 3 v loadfregulationf(v out f=f1.8v) load current ( ma ) o u t p u t v o l t a g e ( v ) 1 . 77 1 . 78 1 . 79 1 . 80 1 . 81 1 . 82 1 . 83 0 100 200 300 400 500 25 c 85 c - 40 c - 40 c v in ( v ) v o u t ( v ) i out = 200 ma 25 c 85 c 1 . 77 1 . 78 1 . 79 1 . 80 1 . 81 1 . 82 1 . 83 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 linefregulationf(v outf =1.8v) v in ( v ) e f f i c i e n c y ( % ) i out = 200 ma - 40 c 25 c 85 c 76 79 82 85 88 91 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 efciencyfvs.fv in f(v outf =1.8v) typical characteristics (continued)
SC202A 7 typical characteristics (continued) lightfloadfswitchingffv out f=f1.8v time (400n s?div) s?div) ?div) v lx (5v/div) v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f1.0v time (400n s?div) s?div) ?div) v lx (5v/div) v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f2.8v time (400n s?div) s?div) ?div) v lx (5v/div) v out (50mv/div) i lx (200ma/div) lightfloadfswitchingffv out f=f3.3v time (400n s?div) s?div) ?div) v lx (5v/div) v out (50mv/div) i lx (200ma/div) heavyfloadfswitchingffv out f=f1.0v time (200n s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v lx (5v/div) heavyfloadfswitchingffv out f=f1.8v time (200n s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v lx (5v/div)
SC202A 8 typical characteristics (continued) heavyfloadfswitchingffv out f=f2.8v time (200n s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v lx (5v/div) heavyfloadfswitchingffv out f=f3.3v time (200n s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v lx (5v/div) heavyfloadfsoft-start time (40 s?div) s?div) ?div) v out (1.0v/div) i in (200ma/div) i lx (500ma/div) lightfloadfsoft-start time (40 s?div) s?div) ?div) v out (1.0v/div) i in (200ma/div) i lx (500ma/div) loadftransientfresponseff25ftof90ma time (20 s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) i load (50ma/div) loadftransientfresponseff25ftof500ma time (20 s?div) s?div) ?div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) i load = 10ma i load = 500ma
SC202A 9 typical characteristics (continued) loadftransientfresponseff200ftof500ma time (20 s?div) s?div) ?div) i lx (500ma/div) v out (100mv/div) i load (500ma/div) lineftransientfresponseffpwm time (400 s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v in (500mv/div) vidftransientfresponseffpwm time (20 s?div) s?div) ?div) v ctl2 (2v/div) v out (500mv/div) i lx (500ma/div) 1.2v to 1.8v transition vidftransientfresponseffpsave time (20 s?div) s?div) ?div) v ctl2 (2v/div) v out (500mv/div) i lx (500ma/div) 1.2v to 1.8v transition lineftransientfresponseffpsave time (400 s?div) s?div) ?div) i lx (200ma/div) v out (50mv/div) v in (500mv/div) shutdownftransientfresponsef time (20 s?div) s?div) ?div) i lx (500ma/div) v out (2v/div) v ctl3-0 (2v/div) 4.0v to 3.5v using li-ion battery 4.0v to 3.5v using li-ion battery
SC202A 10 pin descriptions pin pin name pin function 1, 2, 3 lx switching node sense pin for test purposes only 4 sns output sense pin connect to output capacitor for proper sensing of output voltage. 5 ctl3 control bit 3 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl3 is pulled above the logic high threshold. 6 ctl0 control bit 0 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl0 is pulled above the logic high threshold. 7 ctl1 control bit 1 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl1 is pulled above the logic high threshold. 8 c tl2 control bit 2 see table 1, page 2, for decoding. this pin has a weak pull-down resistor (> 1m ) in place at reset that is removed when ctl2 is pulled above the logic high threshold. 9 in input power supply pin connect a bypass capacitor from this pin to gnd. 10 gnd ground reference and power ground for the SC202A 11, 12, 13 out regulator output pin connect a 10f ceramic capacitor to this pin for proper fltering.
SC202A 11 block diagram control logic plimit amp current amp nlimit amp osc & slope generator pwm comp error amp 500 mv ref ctl 2 ctl 1 ctl 0 sns ctl 3 gnd out in voltage select 10 b 9 6 4 7 8 5 psave comp a = pins 1 , 2 , 3 b = pins 11 , 12 , 13 lx a 1 h
SC202A 12 general description the SC202A is a synchronous step-down pwm (pulse width modulated) dc-dc regulator utilizing a 3.5mhz fxed-frequency voltage-mode architecture and an inter - nal 1 h inductor. the device is designed to operate in fxed-frequency pwm mode and enter psave (power save) mode utilizing pulse frequency modulation under light load conditions for maximizing efciency. two capacitors are the only external components required one for input decoupling and one for output fltering. the output voltage is programmable, eliminating the need for exter - nal programming resistors. loop compensation is also internal, eliminating the need for external components to control stability. programmable output voltage the SC202A has 15 fxed output voltage levels which can be individually selected by programming the ctl control pins (ctl3-0 see table 1 on page 2 for settings). the device is disabled whenever all four ctl pins are pulled low and enabled whenever at least one of the ctl pins is pulled high. this confguration eliminates the need for a dedicated enable pin. each ctl pin is internally pulled down via 1m if v in is below 1.5v or if the voltage on the control pin is below the input high voltage. this ensures that the output is disabled when power is applied if there are no inputs to the ctl pins. each weak pull-down is dis - abled whenever its pin is pulled high and remains disabled until all ctl pins are pulled low. the output voltage can be set using diferent methods. if a static output voltage is required, the ctl pins can be tied to either in or gnd to set the desired voltage when - ever power is applied at in. if enable control is required, each ctl pin can be tied to either gnd or to a micropro - cessor i/o line to create the desired control code whenever the control signal is forced high. this method is equivalent to using the ctl pins collectively as a single enable pin. a third option is to connect each of the four ctl pins to individual microprocessor i/o lines. any of the 15 output voltages can be programmed using this method. if only two output voltages are needed, the ctl pins can be com - bined in a way that will reduce the number of i/o lines to 1, 2, or 3, depending on the control code for each desired voltage. dynamic output voltage adjustment dynamically changing the ctl pins allows dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. this should done using specifc procedures. attention needs to be made so that applying all zeros in a very short period to the ctl pins when changing the output voltage will temporarily disable the device. therefore it is important to avoid these combinations of all zero when dynamically chang - ing the ctl levels. for example, when the ctls change from 0001 to 0010 (0.8v to 1.2v), a transitional state of 0000 (shut down) state might occur in a very short period of time, which could result the device to be disabled unintentionally. in order to achieve such operation, the correct logic transition stages should be 001000110001 (1v1.2v0.8v). the 0011 (1.2v) state should be kept short to prevent from the 0000 state. if the output voltage level is not within the specifed the ctl voltage levels, the resistor divider ratio can be switched by a logic voltage level through an external mosfet to achieve the dynamic output voltage transition. secondly, when the ctl pin is toggled for the output voltage to increase, the regulator will increase the induc - tor current and force the output voltage follow. when the ctl pin is toggled for the output voltage to decrease, the regulator will force the output voltage go down immediately (at heavy load conditions) when the device is in ccm. if the device is in dcm operation (the inductor current does not go negative) then the output voltage will go down as the load current drains the output capacitor. adjustable output voltage selection if an output voltage other than one of the 15 program - mable settings is needed, an external resistor divider network can be added to the SC202A to adjust the output voltage setting. this network scales the output based on the resistor ratio and the programmed output setting. applications information
SC202A 13 the resistor values can be determined using the following equation. 1 fb sns 2 fb 2 fb 1 fb set out r i r r r v v u ? ? o ? ? a u where v out is the desired output voltage, v set is the voltage setting selected by the ctl pins, r fb1 is the resistor between the output capacitor and the sns pin, r fb2 is the resistor between the sns pin and ground, and i sns is the leakage current into the sns pin during normal operation. the current into the sns pin is typically 1a, so the last term of the equation can be neglected if the current through r fb2 is much larger than 1a. selecting a resistor value of 10k or lower will simplify the design. if i sns is neglected and r fb2 is fxed, r fb1 can be determined using the following equation. set set out 2 fb 1 fb v v v r r u inserting resistance in the feedback loop will adversely afect the systems transient performance if feed-forward capacitance is not included in the circuit. the circuit in figure 1 illustrates how the resistor divider and feed- forward capacitor can be added to the SC202A schematic. v out sc 202 a in ctl 3 ctl 2 ctl 1 ctl 0 sns out gnd v in c o ut c in enable c ff r fb 1 r fb 2 figuref1fCfapplicationfcircuitfwithfexternalfresistors the value of feed-forward capacitance needed can be determined using the following equation. 5 . 0 v v v r 5 . 0 v v 10 4 c set set out 1 fb 2 out set 6 ff u u to simplify the design, it is recommended to program the output setting to 1.0v, use resistor values smaller than 10k, and include a feed-forward capacitance calculated with the previous equation. if the output voltage is set to 1.0v, the previous equation reduces to the following equation. 1 v r 5 . 0 v 10 8 c out 1 fb 2 out 6 ff u u example: an output voltage of 1.3v is desired, but this is not a pro - grammable option. what external component values for figure 1 are needed? solution: to keep the circuit simple, set r fb2 to 10k so current into the sns pin can be neglected and set the ctl3-0 pins to 0010 (1.0v setting). the necessary compo - nent values for this situation are shown by the following equations. : u k 3 v v v r r set set out 2 fb 1 fb nf 69 . 5 1 v r 5 . 0 v 10 8 c out 1 fb 2 out 6 ff u u pwm operation normal pwm operation occurs when the output load current exceeds the psave threshold. in this mode, the pmos high side switch is activated with the duty cycle required to produce the output voltage programmed by the ctl pins. an internal synchronous nmos rectifer eliminates the need for an external schottky diode on the lx pin. the duty cycle (percentage of time pmos is active) increases as v in decreases to maintain output voltage regulation. as the input voltage approaches the programmed output voltage, the duty cycle approaches 100% (pmos always on) and the device enters a pass- through mode until the input voltage increases or the load decreases enough to allow pwm switching to resume. power save mode operation when the load current decreases below the psave threshold, pwm switching stops and the device auto - matically enters psave mode. this threshold varies depending on the input voltage and output voltage applications information (continued)
SC202A 14 setting, optimizing efciency for all possible load currents in pwm or psave mode. while in psave mode, output voltage regulation is controlled by a series of switching bursts. during a burst, the inductor current is limited to a peak value which controls the on-time of the pmos switch. after reaching this peak, the pmos switch is disabled and the inductor current decreases to near 0ma. switching bursts continue until the output voltage climbs to v out +2.5% or until the psave current limit is reached. switching is then stopped to eliminate switching losses, enhancing overall efficiency. switching resumes when the output voltage reaches the lower threshold of v out and continues until the upper threshold again is reached. note that the output voltage is regulated hysteretically while in psave mode between v out and v out + 2.5%. the period and duty cycle while in psave mode are solely determined by v in and v out until pwm mode resumes. this can result in the switching frequency being much lower than the pwm mode frequency. if the output load current increases enough to cause v out to decrease below the psave exit threshold (v out -2%), the device automatically exits psave and operates in continu - ous pwm mode. note that the psave high and low threshold levels are both set at or above v out to minimize undershoot when the SC202A exits psave. figure 2 illus - trates the transitions from pwm mode to psave mode and back to pwm mode. v out - 2 % v out v out + 2 . 5 % load demand ( i out ) burst off v lx time pwm mode at medium / high load psave mode at light load pwm mode at medium / high load psave exit figuref2fftransitionsfbetweenfpwmfandfpsavefmodes applications information (continued) protection features the SC202A provides the following protection features: soft-start operation over-voltage protection current limit thermal shutdown under-voltage lockout soft-start the soft-start sequence is activated after a transition from an all zeros ctl code to a non-zero ctl code enables the device. at start-up, the pmos current limit is stepped through four levels: 25%, 40%, 60%, and 100%. each step is maintained for 60s following an internal reference start up of 20s, resulting in a total nominal start-up period of 260s. if v out reaches 90% of the target within the frst 2 steps, the device continues in psave mode at the end of soft-start; otherwise, it goes into pwm mode. note the v out ripple in psave mode can be larger than the ripple in pwm mode. over-voltage protection over-voltage protection ensures the output voltage does not rise to a level that could damage its load. when v out exceeds the regulation voltage by 15%, the pwm drive is disabled. switching does not resume until v out has fallen below the regulation voltage by 2%. current limit the SC202A switching stage is protected by a current limit function. if the output load exceeds the pmos current limit for 32 consecutive switching cycles, the device enters fold-back current limit mode and the output current is limited to approximately 150ma. under these conditions, the output voltage will be the product of i fb-lim and the load resistance. the load must fall below i fb-lim for the device to exit fold-back current limit mode. this function makes the device capable of sustaining an indefnite short circuit on its output under fault conditions. thermal shutdown the SC202A has a thermal shutdown feature to protect the device if the junction temperature exceeds 160c. during thermal shutdown, the pmos and nmos switches are both disabled, tri-stating the lx output. when the junction temperature drops by the hysteresis value (20c), ? ? ? ? ?
SC202A 15 the device goes through the soft-start process and resumes normal operation. under-voltage lockout uvlo (under-voltage lockout) activates when the supply voltage drops below the falling uvlo threshold. this pre - vents the device from entering an ambiguous state in which regulation cannot be maintained. hysteresis of approximately 200mv is included to prevent chattering near the threshold. c out selection the internal voltage loop compensation in the SC202A limits the minimum output capacitor value to 10f. this is due to its infuence on the the loop crossover frequency, phase margin, and gain margin. increasing the output capacitor above this minimum value will reduce the cross - over frequency and provide greater phase margin. capacitors with x7r or x5r ceramic dielectric are recom - mended for their low esr and superior temperature and voltage characteristics. y5v capacitors should not be used as their temperature coefcients make them unsuitable for this application. in addition to ensuring stability, the output capacitor serves other important functions. this capacitor deter - mines the output voltage ripple as capacitance increases, ripple voltage decreases. it also supplies current during a large load step for a few switching cycles until the control loop responds (typically 3 switching cycles). once the loop responds, regulation is restored and the desired output is reached. during the period prior to pwm operation resuming, the relationship between output voltage and output capacitance can be approximated using the following equation. f v i 3 c droop load out u ' u this equation can be used to approximate the minimum output capacitance needed to ensure voltage does not droop below an acceptable level. for example, a load step from 50ma to 400ma requiring droop less than 50mv would require the minimum output capacitance as shown by the following equation. applications information (continued) manufacturer/part no. l (h) dcr max (?) rated current (a) l at rated current (h) dimensions lxwxh (mm) murata lqm2hpn1r0 120% 0.13 1.5 0.78 2.5x2.0x1.2 murata lqh3npn1r0 120% 0.07 1.7 0.78 3.0x3.0x1.5 coilcraft lpo4815 120% 0.036 1.9 0.8 4.8x4.8x1.5 coilcraft lps3010 120% 0.085 1.6 0.7 3.0x3.0x1.0 shielded fdk mipwt3226d1r5 1.530% 0.09 1.2 0.9 3.2x2.6x0.8 fdk mipf2520d1r5 1.530% 0.07 1.5 0.9 3.2x2.6x0.8 tayo yuden ckp32161r5m 1.520% 0.13 1 0.5 3.2x1.6x0.8 f 0 . 6 10 5 . 3 05 . 0 4 . 0 3 c 6 out p u u u in this example, using a standard 10f capacitor would be adequate to keep voltage droop less than the desired limit. note that if the voltage droop limit were decreased from 50mv to 25mv, the output capacitance would need to be increased to at least 12f (twice as much capaci - tance for half the droop). capacitance will decrease from the nominal value when a ceramic capacitor is biased with a dc current, so it is important to select a capacitor whose value exceeds the necessary capacitance value at the pro - grammed output voltage. check the manufacturers capacitance vs. dc voltage graphs when selecting an output capacitor to ensure the capacitance will be adequate. table 2 lists the manufacturers of recommended output capacitor options. table 2 recommended output capacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm188r60j106me47d 1020% x5r 6.3 1.6x0.8x0.8 0603 murata grm21br60j106k 1010% x5r 6.3 2.0x1.25x1.25 0805 taiyo yuden jmk107bj106ma-t 1020% x5r 6.3 1.6x0.8x0.8 0603 tdk c1608x5r0j106mt 1020% x5r 6.3 1.6x0.8x0.8 0603 c in selection the SC202A input source current will appear as a dc supply current with a triangular ripple imposed on it. to prevent large input voltage ripple, a low esr ceramic capacitor is required. a minimum value of 4.7f should be used. it is important to consider the dc voltage coef - cient characteristics when determining the actual required value. for example, a 10f, 6.3v, x5r ceramic capacitor with 5v dc applied may exhibit a capacitance as low as 4.5f. the value of required input capacitance is estimated by determining the acceptable input ripple voltage and
SC202A 16 applications information (continued) calculating the minimum value required for c in using the following equation. f esr i v v v 1 v v c out in out in out in ? ? 1 ? ' ? ? 1 ? the input voltage ripple is at maximum level when the input voltage is twice the output voltage (50% duty cycle scenario). the input capacitor provides a low impedance loop for the edges of pulsed current drawn by the pmos switch. low esr/esl x5r ceramic capacitors are recommended for this function. to minimize stray inductance, the capaci - tor should be placed as close as possible to the in and gnd pins. table 3 lists recommended input capacitor options from diferent manufacturers. tablef3fffrecommendedfinputfcapacitors manufacturer part nunber value (f) type rated voltage (vdc) dimensions lxwxh (mm) case size murata grm1r045 4.710% x5r 6.3 1.6x0.8x0.8 0603 murata grm188r60j106k 1010% x5r 6.3 1.6x0.8x0.8 0603 taiyo yuden jmk107bj475ka 4.710% x5r 6.3 1.6x0.8x0.8 0603 tdk c1608x5r0j475kt 4.710% x5r 6.3 1.6x0.8x0.8 0603 pcb layout considerations the layout diagram in figure 3 shows a recommended pcb top-layer for the SC202A and supporting compo - nents. specifed layout rules must be followed since the layout is critical for achieving the performance specifed in the electrical characteristics table. poor layout can degrade the performance of the dc-dc converter and can contribute to emi problems, ground bounce, and resistive voltage losses. poor regulation and instability can also result. the following guidelines are recommended for designing a pcb layout: c in should be placed as close to the in and gnd pins as possible. this capacitor provides a low impedance loop for the pulsed currents present at the buck converters input. use short wide traces to minimize trace impedance. this will also minimize emi and input voltage ripple by localizing the high frequency current pulses. c out should be connected as closely as possible to the out pin. use a ground plane referenced to the gnd pin. use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. route the output voltage feedback/sense trace (connected to the sns pin) away from the lx node as shown in figure 3 to minimize noise and magnetic interference. minimize the resistance from the out and gnd pins to the load. this will reduce errors in dc regulation due to voltage drops in the traces. the two smaller exposed pads on this package should not be connected to any traces. the area beneath these two pads must be kept clear so that they do not make electrical contact with any traces, including ground. c in ctl 2 ctl 0 ctl 1 ctl 3 lx ( no connection needed ) sns gnd in out 3 . 8 mm 3 . 5 mm sc 202 a these pads should not be electrically connected to the pcb . c out figuref3ffrecommendedfpcbflayoutf 1. 2. 3. 4. 5. 6.
SC202A 17 2.50 2.40 2.60 notes: 0.08 13 0.60 - 0.00 0.80 0.75 0.70 - 0.05 1.00 (0.20) - - 0.10 1.17 2.90 1.27 1.32 3.00 3.10 0.40 bsc 0.40 0.45 0.50 coplanarity applies to the exposed pad as well as the terminals. 2. controlling dimensions are in millimeters (angles in degrees). 1. dimensions e bbb aaa a1 a2 d1 e1 dim n l e d a millimeters max min nom b 0.15 0.20 0.25 seating plane bbb c a b aaa c c pin 1 indicator (laser mark) d e b a a1 a a2 lx7 0.355 0.30 x 45 chamfer e 0.238 e1 see detail a c l c l 0.363 0.684 0.157 0.312 2x 0.200 2x 0.110 8x 0.025 detail a scale: 4/1 1.30 1 2 n 0.800 e/2 0.265 d1 0.95 0.25 d/2 e bxn c l l c 2x outline drawing mlpq-13
SC202A 18 land pattern mlpq-13 this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 2. dim x y h k p g millimeters 0.20 0.80 1.27 0.40 0.75 1.50 dimensions company's manufacturing guidelines are met. 3.10 z land patterns ( solder pads) not required for smaller exposed pads. 3. 1. g 2x 0.110 2x 0.200 8x 0.025 small exposed pads location controlling dimensions are in millimeters (angles in degrees). 4. do not place exposed traces or vias under smaller exposed pads. 0.80 p1 0.157 0.312 0.265 h 0.684 0.363 p1 p 0.355 1.55 c c l c c l (p) 0.55 .250 k x 0.238 z (p) (3.10) 1.30 y 2x
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC202A 19 ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse - quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or elec - trical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners.

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